The SRAM is shared with Intel® CSME as shareable memory. The SRAM is a total of 640 kbytes organized into banks of 32 kB each and is 32-bit wide. The local SRAM block includes both the physical SRAM as well as the controller logic. The local SRAM is used for ISH FW code storage and to read/write operational data. A local boot ROM with FW for initialization is also part of the core. The core supports an in-built local APIC that receives messages from the IOAPIC.

This core provides localized sensor aggregation and data processing, thus off loading the processor and lowering overall platform average power. The ISH is operated by a micro-controller. Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- įrom the Intel® 300 Series and Intel® C240 Series Chipset Family Platform Controller Hub datasheet ISH Micro-Controller section: ISH Micro-Controller

0000:00:14.2 RAM memory : Intel Corporation Device (rev 20)Ĭontrol: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx. The RAM as mapped into the memory region is also particularly small and so is unlikely to be used for anything more than sharing data between devices. According to the proper device name is Tiger Lake-LP Shared SRAM

What slot does ram go in